Dr. Shyamapada Mukherjee




  • B. E, M.Tech,  PhD


My research interests lie primarily in the area of computer-aided-design of integrated circuits, specifically centered in algorithms for placement and routing for high-performance VLSI circuits and different FPGA architectures. In addition to this I have started working in the following areas:

  • Verification and Testing in VLSI  Design
  • Designing IoT devices
  • Machine Learning Applications
  • Gait Analysis
  • Gesture recognition using ML on FPGAs


  1. Shyamapada Mukherjee, Suchismita Roy. Nearly-2-SAT Solutions for Segmented Channel Routing, IEEE Transaction on Computer Aided-Design of Integrated Circuits and Systems, Volume 35, Issue 1, Jan 2016, Pages 128-140. (SCI)
  2. Shyamapada Mukherjee, Suchismita Roy, SAT based solutions for detailed routing of island style FPGA architectures, Microelectronics Journal, Elsevier, Volume 46, Issue 8, August 2015, Pages 706-715. (SCI)
  3. Shyamapada Mukherjee, Suchismita Roy. Via-Aware Dogleg Router using Boolean Satisfiability, J CIRCUIT SYST COMP 26, 1750064 (2017) [24 pages] DOI: http://dx.doi.org/10.1142/S0218126617500645. (SCI)
  4. Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy. 2013. Congestion Balancing Global Router. VLSI Design and Test, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2013, Volume 382, Pages 223-232. (SCOPUS)
  5. Shyamapada Mukherjee, Suchismita Roy. 2012. Testing the Effect of different Switch Box Architectures on Detailed Routing in FPGA. International Journal of Computer Applications, 2012, Volume iC3S, Number 5, pages 1-5.
  6. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee. 2016. SAT based Rectilinear Steiner Tree Construction. 2nd International Conference on Applied and Theoretical Computing and Communication Technology , IEEE, July 2016.
  7. Shyamapada Mukherjee, Suchismita Roy. 2015. Multi Terminal Nets Routing for Island Style FPGAs using Nearly-2-SAT-Computation. 19th International Symposium on VLSI Design and Test (VDAT), IEEE, June 2015, pages 1-6 .
  8. Shyamapada Mukherjee, Suchismita Roy. 2014. Effect of Relaxed Switching Structures on Detailed Routing of Island Style FPGA. International Conference on Information and Communication Technology for Competitive Strategies, ACM, 2014, Article No. 35, pages 35:1–35:6
  9. Shyamapada Mukherjee, Suchismita Roy. 2013. Graph Colouring Based Multi Pin Nets Detailed Routing for Island Style FPGAs using SAT. International Advance Computing Conference, IEEE, 2013, pages 308-312.
  10. Shyamapada Mukherjee, Suchismita Roy. 2010. SAT Based Multi Pin Net Detailed Routing For FPGA. International Symposium on Electronic System Design, IEEE Computer Society. 2010, Pages 141-146.
  11. Sharbani Purakayastha, Shyamapada Mukherjee, Lookahead Legalization Based Global Placement for Heterogeneous FPGAs. 7th International Symposium on Embeded Computing and System Design. IEEE, 18th-20th Decmber 2017, Durgapur, India.( Accepted) 
  12. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, K-Nearest Neighbour Approach with SAT for Rectilinear Steiner Tree Construction. 7th International Symposium on Embeded Computing and System Design. IEEE, 18th-20th Decmber 2017, Durgapur, India.( Accepted) 
  13. Prasun Datta and Shyamapada Mukherjee, Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model. 2nd International conference on Electronics, Communication and Aerospace Technology (ICECA 2018), IEEE, 29th-31th March 2018, Coimbatore. ( Accepted) 
  14. Prasun Datta and Shyamapada Mukherjee, GPSAT: A SAT based Global Placement for Large Scale Mixed-size Designs. International Conference on Intelligent Autonomus Systems (ICIAS 2018), IEEE, SCOPUS, 1st-3rd March, Singapore, 2018.  (Accepted)

Papers Under Review

  1. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, Rectilinear Steiner Tree Construction Techniques using PB-SAT based Methodology, Integration, the VLSI Journal.
  2. Prasun Datta and Shyamapada Mukherjee, A Methodological Architecture Aware Routability-Driven Placement for Large Scale Mixed-Size Design Circuits, Integration, the VLSI Journal.
  3. Prasun Datta and Shyamapada Mukherjee, IPplacer: An Efficient 0-1 Integer Programming based Placement for VLSI Circuits. (Conference)
  4. Prasun Datta and Shyamapada Mukherjee, Routability Aware Placer Using SAT. (ACM Transactions on Design Automation of Electronic Systems)
  5. Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method using PB-SAT.


  1. Assistant Professor, Department of Computer Science and Engineering, National Institute of Technology, Silchar, India.July, 2016–till Date
  2. Assistant Professor, Department of Computer Science and Information Systems, Birla Institute of Technology and Science Pilani, Rajasthan India. Dec, 2015–17th July, 2016
  3. Assistant Professor, Department of Computer Application, Dr. B.C. Roy Engineering College, Durgapur, India. March, 2007–Dec, 2015
  4. Lecturer, Department of Computer Science & Engineering, Bengal Institute of Technology & Management, Santiniketan, India. August,2005–February,2007.


  • Theory of Computation
  • Compiler Design
  • Design and Analysis of Algorithms
  • Computer Architecture
  • Operating Systems
  • Computer Networks
  • VLSI Design
  • Advanced Data Structure
  • Introduction to Computing 
  • Switching Theory and Digital Electronics
  • B. Tech: Palm Vein Pattern Authentication System 
  • M. Tech: PIGP: Plant Inspired Global Placement of Mixed-sized Hierarchical VLSI Circuits


                   1. Alok Das (Completed)
                       2. Asish Singh (On going)
                  1. Sharbani Purkayastha (On going)
                      2. Rohit Pratap Singh (On going)
                      3. Prasun Datta (On going)
                      4. Sudeshna Kundu(On going)
                      5. Yagnyasenee Sengupta(On going)
Faculty Advisor: CSE 3rd SEM (Jan – June 2017)
Faculty Advisor: CSE 5th SEM (July – Dec 2017)
BTech Coordinator (July 2017 – tilldate)
DUPC Committee member
MTech Admission Committee member
MTech Syllabus Committee member
Time-Table coordinator