- Yagnyasenee Sengupta, Shyamapada Mukherjee, A Reward-based Framework for Recovery and Utilization of Recyclable Wastes using Blockchain, OITS International Conference on Information Technology, IEEE (Accepted)
- Agneesh Dasgupta, Shyamapada Mukherjee, An Approach for Transparent Logistic Solution for Life Saving Medicines and Essential Goods using IoT and Blockchain, 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (IEEE) (Accepted)
- Manish Sarmah, Shruti Saxena, and Shyamapada Mukherjee, A Decentralized Crowdfunding Solution on Top of the Ethereum Blockchain, IEEE SILICON 2022. (Accepted)
- Yagnyasenee Sengupta, Shyamapada Mukherjee, Rahul Dutta, Sukriti Bhattacharya, A Blockchain Based Approach Using Smart Contracts to Develop a Smart Waste Management System, International Journal of Environmental Science and Technology, Springer. 2021. https://doi.org/10.1007/s13762-021-03507-8
- Gupta Y.S., Mukherjee S. (2020) A Study on Smart Cities Using Blockchain. In: Dawn S., Balas V., Esposito A., Gope S. (eds) Intelligent Techniques and Applications in Science and Technology. ICIMSAT 2019. Learning and Analytics in Intelligent Systems, vol 12. Springer, Cham.
INTERNET OF THINGS & CYBER PHYSICAL SYSTEMS:
- S. Banerjee. S. Mukherjee, B. Purkayastha, A Study of Fog Computing Technology Serving Internet of Things (IoT). In: El¸ci A., Sa P., Modi C., Olague G., Sahoo M., Bakshi S. (eds) Smart Computing Paradigms: New Progresses and Challenges. Advances in Intelligent Systems and Computing, vol 767. Springer, Singapore.
- Yagnyasenee Sen Gupta and Shyamapada Mukherjee, A Survey on Security Issues in Cyber Physical Systems. International Journal of Computational Intelligence IoT, Vol. 1, No. 2, 2018.
AI & NATURAL LANGUAGE PROCESSING:
- Yagnyasenee Sengupta, Shyapada Mukherjee, An Ensembling Approach for Efficient Waste Classification, IEEE SILICON 2022. (Accepted)
- Sumanta Banerjee and Shyamapada Mukherjee. (2022) A Comparative Study of Seasonal-ARIMA and RNN (LSTM) on Time Series Temperature Data Forecasting. Pervasive Computing and Social Networking. Lecture Notes in Networks and Systems, vol 317. Springer, Singapore. https://doi.org/10.1007/978-981-16-5640-8_25
- Mukherjee, N. Shivam, A. Gangwal, L. Khaitan and A. J. Das, “Spoken Language Recognition Using CNN,” 2019 International Conference on Information Technology (ICIT), Bhubaneswar, India, 2019, pp. 37-41.
- S. Kundu, S. Roy and S. Mukherjee, “K-nearest neighbour (KNN) approach using SAT based for rectilinear steiner tree construction,” 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017, pp. 1-5.
- Mukherjee, K. Chaudhary, P. Jain and B. Paul, “Gait Recognition using Segmented Motion Flow Energy Image,” 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-6
VLSI & FPGAs & INTEGRATED CIRCUIT LAYOUT:
- S. Purkayastha, Shyamapada Mukherjee, PHetDP: A Placement Algorithm for Heterogeneous
FPGAs with Delayed Packing. Journal of Circuits, Systems, and Signal Processing, Springer. (Accepted)
- Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, Congestion-aware Rectilinear Steiner
Tree Construction using PB-SAT, Journal of Circuit, Systems and Computers, World Scientific Journal, Vol. 31, No. 09, 2250165 (2022)
- S. Mukherjee, S. Purkayastha. Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAs. Arab J Sci Eng (2021). https://doi.org/10.1007/s13369-021-06176-4.
- Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee (2021) An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method Using PB-SAT, IETE Journal of Research, Taylor and Francis. 2021 DOI: 10.1080/03772063.2021.1967790.
- Prasun Datta, Shyamapada Mukherjee. OptiPlace: optimized placement solution for mixed-size designs. Analog Integr Circ Sig Process 109, 501–515 (2021). https://doi.org/10.1007/s10470-021-01864-5.
- Prasun Datta and Shyamapada Mukherjee, ”Architecture-aware routability-driven placer for largescale mixed-size designs,” in IET Circuits, Devices Systems, vol. 13, no. 8, pp. 1209-1220, 11 2019. DOI: 10.1049/iet-cds.2018.5518
- Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, Rectilinear Steiner Tree Construction Techniques using PB-SAT based Methodology, Journal of Circuit, Systems and Computers, World Scientific Journal.Vol 29 No. 4. 2020. https://doi.org/10.1142/S0218126620500577.
- Shyamapada Mukherjee, Suchismita Roy. Nearly-2-SAT Solutions for Segmented Channel Routing, IEEE Transaction on Computer Aided-Design of Integrated Circuits and Systems, Volume 35, Issue 1, Jan 2016, Pages 128-140.
- Shyamapada Mukherjee, Suchismita Roy, SAT based solutions for detailed routing of island style FPGA architectures, Microelectronics Journal, Elsevier, Volume 46, Issue 8, August 2015, Pages 706-715.
- Shyamapada Mukherjee, Suchismita Roy. Via-Aware Dogleg Router using Boolean Satisfiability, Journal of Circuits, Systems, and Computers, Vol. 26, No. 04, 1750064 (2017).
- S. Mukherjee, S. Saikia, S. Anand, R. Chouhan, H. Das. A Counter Measure to Prevent Timing-based Side-Channel Attack on FPGA, 2021 6th International Conference on Communication and Electronics Systems (ICCES), 2021, pp. 983-988, doi: 10.1109/ICCES51350.2021.9489054.
- S. Purkayastha and S. Mukherjee. Lookahead legalization based global placement for heterogeneous FPGAs,” 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017, pp. 1-5.
- S. Kundu, S. Roy and S. Mukherjee. K-nearest neighbour (KNN) approach using SAT based for rectilinear steiner tree construction. 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017, pp. 1-5.
- Prasun Datta and Shyamapada Mukherjee. Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model. 2nd International conference on Electronics, Communication and Aerospace Technology (ICECA 2018), IEEE, 29th-31th March 2018, Coimbatore, Page s: 1577 – 1581.
- Prasun Datta and Shyamapada Mukherjee. GPSAT: A SAT based Global Placement for Large Scale Mixed-size Designs. International Conference on Intelligent Autonomus Systems (ICIAS 2018), IEEE, SCOPUS, 1st-3rd March, Singapore, 2018, pp. 77-81.
- Prasun Datta and Shyamapada Mukherjee, IPplacer: An Efficient 0-1 Integer Programming based Placement for VLSI Circuits. 9th ICCCNT, IISc Bengaluru. 10-12 July 2018. Pages: 1 – 7.
- Shyamapada Mukherjee, Arun Nainwal, Chinmoy Shekhar Das, Sharbani Purkayastha, An alternate Algorithmic Approach to VLSI Placement. 9th ICCCNT, IISc Bengaluru. 10-12 July, 2018.
- Prasun Datta and Shyamapada Mukherjee. “Routability-driven Placement for Mixed-size Designs using Design-hierarchy and Pin Information,” 2019 International Conference on Automation, Computational and Technology Management (ICACTM), London, United Kingdom, 2019, pp. 424-430.
- Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee. 2016. SAT based Rectilinear Steiner Tree Construction. 2nd International Conference on Applied and Theoritical Computing and Communication Technology , IEEE, July 2016.
- Shyamapada Mukherjee, Suchismita Roy. 2015. Multi Terminal Nets Routing for Island Style FPGAs using Nearly-2-SAT-Computation. 19th International Symposium on VLSI Design and Test (VDAT), IEEE, June 2015, pages 1-6.
- Shyamapada Mukherjee, Suchismita Roy. 2014. Effect of Relaxed Switching Structures on Detailed Routing of Island Style FPGA. International Conference on Information and Communication Technology for Competitive Strategies, ACM, 2014, Article No. 35, pages 35:1–35:6.
- Shyamapada Mukherjee, Suchismita Roy. 2013. Graph Colouring Based Multi Pin Nets Detailed Routing for Island Style FPGAs using SAT. International Advance Computing Conference, IEEE, 2013, pages 308-312.
- Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy. 2013. Congestion Balancing Global Router. VLSI Design and Test, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2013, Volume 382, Pages 223-232.
- Shyamapada Mukherjee, Suchismita Roy. 2010. SAT Based Multi Pin Net Detailed Routing For FPGA. International Symposium on Electronic System Design, IEEE Computer Society. 2010, Pages 141-146.
- Shyamapada Mukherjee, Suchismita Roy. 2012. Testing the Effect of different Switch Box Architectures on Detailed Routing in FPGA. International Journal of Computer Applications, 2012, Volume iC3S, Number 5, pages 1-5.