Dr. Shyamapada Mukherjee

Dr. Shyamapada MukherjeeAssistant Professor Grade IRoom No. 26, Department of CSENIT Silchar, Assam, India 788010Email: shyama[at]cse[dot]nits[dot]ac[dot]in                      shyamamukherji[at]gmail[dot]com
ACADEMIC QUALIFICATIONS :  B. E, MTech,  PhD
RESEARCH INTEREST: My research interests lie primarily in the area of computer-aided-design of integrated circuits, specifically centered in algorithms for placement and routing for high-performance VLSI circuits and different FPGA architectures. In addition to this I have started working in the following areas:

  • Verification and Testing in VLSI  Design
  • Designing IoT devices
  • Machine Learning Applications
  • Information Retrieval
  • Application of Blockchain Technology
  • Hardware Security
  • Cyber Physical Systems

Though this looks a long list but all the fields are very related and Cyber Physical System is an area of research where all these fields converge.

LAB ESTABLISHMENT: Internet of Things lab has been set up in the department of CSE of NIT Silchar. This laboratory has been set up recently and a team consisting of PhD, MTech, and BTech students are working on different problems in this lab. This lab is equipped with many components for implementing and exploring various IoT related problems. Students having interest in working in IoT and Cyber Physical Systems can apply for internship by writing emails to me.
PUBLICATIONS:

  • Prasun Datta and Shyamapada Mukherjee, “OptiPlace: Optimized Placement Solution for Mixed-size Designs”, in Analog Integrated Circuits and Signal Processing,  Springer Nature, 2021. (Accepted)
  • Prasun Datta and Shyamapada Mukherjee, ”Architecture-aware routability-driven placer for largescale mixed-size designs,” in IET Circuits, Devices Systems, vol. 13, no. 8, pp. 1209-1220, 11 2019.
  • Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee, Rectilinear Steiner Tree Construction Techniques using PB-SAT based Methodology, Journal of Circuit, Systems and Computers, World Scientific Journal.Vol 29 No. 4. 2020.
  • Shyamapada Mukherjee, Suchismita Roy. Nearly-2-SAT Solutions for Segmented Channel Routing, IEEE Transaction on Computer Aided-Design of Integrated Circuits and Systems, Volume 35, Issue 1, Jan 2016, Pages 128-140.
  • Shyamapada Mukherjee, Suchismita Roy, SAT based solutions for detailed routing of island style FPGA architectures, Microelectronics Journal, Elsevier, Volume 46, Issue 8, August 2015, Pages 706-715.
  • Shyamapada Mukherjee, Suchismita Roy. Via-Aware Dogleg Router using Boolean Satisfiability, Journal of Circuits, Systems, and Computers 26, 1750064 (2017) [24 pages].
  • Sumanta Banerjee and Shyamapada Mukherjee, “A Comparative Study of Seasonal-ARIMA and RNN (LSTM) on Time Series Temperature Data Forecasting”, International Conference on Pervasive Computing and Social Networking, 2021, Spinger. (Accepted).
  • Mukherjee, N. Shivam, A. Gangwal, L. Khaitan and A. J. Das, “Spoken Language Recognition Using CNN,” 2019 International Conference on Information Technology (ICIT), Bhubaneswar, India, 2019, pp. 37-41.
  • Gupta Y.S., Mukherjee S. (2020) A Study on Smart Cities Using Blockchain. In: Dawn S., Balas V., Esposito A., Gope S. (eds) Intelligent Techniques and Applications in Science and Technology. ICIMSAT 2019. Learning and Analytics in Intelligent Systems, vol 12. Springer, Cham.
  • S. Purkayastha and S. Mukherjee, Lookahead legalization based global placement for heterogeneous FPGAs,” 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017, pp. 1-5.
  • S. Kundu, S. Roy and S. Mukherjee, “K-nearest neighbour (KNN) approach using SAT based for rectilinear steiner tree construction,” 2017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, India, 2017, pp. 1-5.
  • Prasun Datta and Shyamapada Mukherjee, Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model. 2nd International conference on Electronics, Communication and Aerospace Technology (ICECA 2018), IEEE, 29th-31th March 2018, Coimbatore, Page s: 1577 – 1581.
  • Prasun Datta and Shyamapada Mukherjee, GPSAT: A SAT based Global Placement for Large Scale Mixed-size Designs. International Conference on Intelligent Autonomus Systems (ICIAS 2018), IEEE, SCOPUS, 1st-3rd March, Singapore, 2018, pp. 77-81.
  • Banerjee, S . Mukherjee, B. Purkayastha, A Study of Fog Computing Technology Serving Internet of Things (IoT). In: El¸ci A., Sa P., Modi C., Olague G., Sahoo M., Bakshi S. (eds) Smart Computing Paradigms: New Progresses and Challenges. Advances in Intelligent Systems and Computing, vol 767. Springer, Singapore.
  • Prasun Datta and Shyamapada Mukherjee, IPplacer: An Efficient 0-1 Integer Programming based Placement for VLSI Circuits. 9th ICCCNT, IISc Bengaluru. 10-12 July 2018. Pages: 1 – 7
  • Shyamapada Mukherjee, Arun Nainwal, Chinmoy Shekhar Das, Sharbani Purkayastha, An alternate Algorithmic Approach to VLSI Placement. 9th ICCCNT, IISc Bengaluru. 10-12 July, 2018.
  • Yagnyasenee Sen Gupta and Shyamapada Mukherjee, A Survey on Security Issues in Cyber Physical Systems. International Journal of Computational Intelligence IoT, Vol. 1, No. 2, 2018.
  • Mukherjee, K. Chaudhary, P. Jain and B. Paul, “Gait Recognition using Segmented Motion Flow Energy Image,” 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-6.
  • Datta and S. Mukherjee, “Routability-driven Placement for Mixed-size Designs using Design-hierarchy and Pin Information,” 2019 International Conference on Automation, Computational and Technology Management (ICACTM), London, United Kingdom, 2019, pp. 424-430.
  • Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee. 2016. SAT based Rectilinear Steiner Tree Construction. 2nd International Conference on Applied and Theoritical Computing and Communication Technology , IEEE, July 2016.
  • Shyamapada Mukherjee, Suchismita Roy. 2015. Multi Terminal Nets Routing for Island Style FPGAs using Nearly-2-SAT-Computation. 19th International Symposium on VLSI Design and Test (VDAT), IEEE, June 2015, pages 1-6.
  • Shyamapada Mukherjee, Suchismita Roy. 2014. Effect of Relaxed Switching Structures on Detailed Routing of Island Style FPGA. International Conference on Information and Communication Technology for Competitive Strategies, ACM, 2014, Article No. 35, pages 35:1–35:6
  • Shyamapada Mukherjee, Suchismita Roy. 2013. Graph Colouring Based Multi Pin Nets Detailed Routing for Island Style FPGAs using SAT. International Advance Computing Conference, IEEE, 2013, pages 308-312.
  • Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy. 2013. Congestion Balancing Global Router. VLSI Design and Test, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2013, Volume 382, Pages 223-232.
  • Shyamapada Mukherjee, Suchismita Roy. 2010. SAT Based Multi Pin Net Detailed Routing For FPGA. International Symposium on Electronic System Design, IEEE Computer Society. 2010, Pages 141-146.
  • Shyamapada Mukherjee, Suchismita Roy. 2012. Testing the Effect of different Switch Box Architectures on Detailed Routing in FPGA. International Journal of Computer Applications, 2012, Volume iC3S, Number 5, pages 1-5.
BOOK CHAPTERS:

  1. Shyamapada Mukherjee, A Cyber Physical System Model for Autonomous Tolling Booths, Springer. 2021.(Accepted)
  2. Shyamapada Mukherjee, Ayush Agarwala, and Rishab AgarwalaA Review on Generative Adversarial Networks. Springer. 2021. (Accepted)
  3. Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy. 2013. Congestion Balancing Global Router. VLSI Design and Test, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2013, Volume 382, Pages 223-232.
  4. Sumanta Banerjee, Shyamapada Mukherjee, B. Purkayastha, A Study of Fog Computing Technology Serving Internet of Things (IoT). In: El¸ci A., Sa P., Modi C., Olague G., Sahoo M., Bakshi S. (eds) Smart Computing Paradigms: New Progresses and Challenges. Advances in Intelligent Systems and Computing, vol 767. Springer, Singapore.
  5. Y.S. Gupta, Shyamapada Mukherjee  (2020) A Study on Smart Cities Using Blockchain. In: Dawn S., Balas V., Esposito A., Gope S. (eds) Intelligent Techniques and Applications in Science and Technology. ICIMSAT 2019. Learning and Analytics in Intelligent Systems, vol 12. Springer, Cham.
WORKSHOP/SEMINAR ORGANIZED: 

  1. International Workshop on Modeling, Simulation and Soft Computing (IWMSSC 2018) during August 10-14, 2018, under TEQIP-III, NIT Silchar, as coordinator
  2. Design and Deployment of Cyber Physical Systems Registration (DDCPS 2018) during September 17th -21st, 2018. as coordinator
  3. Visit of Professor Alain Tremeau, University of Jean Monnet, France to NIT Silchar  for Research collaboration during November 15-19, 2018 as coordinator.
  4. One day seminar on Data Science by Dr. Emmett Lentilucci, Rochester Institute of Technology on 25th January, 2018.
CONFERENCE COMMITTEES:

  1. Program Chair, ICACNI 2018
  2. Member, BigDML 2019
  3. Hospitality Chair, FRSM 2020
  4. Technical Program Committee MIND 2020
  5. Session Chair, ICRTECS 2019
  6. Session Chair, ICACTM 2019
FOREIGN VISIT:

  1. Visited Nanyang Technological University Singapore in March 2018.
  2. Visited University of London, London UK in April-May 2019
  3. Visited Paris, France in April 2019
  4. Visited Zurich, Switzerland in April-May 2019
JOURNAL REVIEWED:

  1. IEEE Transaction on Computer Aided Design of integrated circuits and systems
  2. Microelectronics Journal, Elsevier,
  3. ACM Transaction on design automation of electronic systems
TEACHING EXPERIENCE:

  1. From July 2006  to February 2007 , Lecturer in Bengal Institute of Technology and Management Santiniketan, West Bengal.
  2. From March 2007 to December 2015, Assistant Professor in Dr. B. C. Roy Engineering College, Durgapur, West Bengal.
  3. From December 2015 to July 2016, Assistant Professor in Birla Institute of Science and Technology Pilani, Rajasthan.
  4. From July 2016 to till now, Assistant Professor in  National Institute of  Technology Silchar, Assam.
COURSES TAUGHT: 

  1. Theory of Computation
  2. Compiler Design
  3. Design and Analysis of Algorithms
  4. Computer Architecture
  5. Operating Systems  
  6. Computer Networks
  7. VLSI Design
  8. Advanced Data Structure
  9. Introduction to Computing
  10. Switching Theory and Digital Electronics
  11. System Analysis and Design
  12. Data Structure
PhD GUIDED: 

  1. Sharbani Purkayastha (On going): Problem: Routability-aware Placement solutions for Heterogeneous FPGAs using congestion estimation by Machine learning techniques.
  2. Prasun Datta (On going): Problem: Placement solutions for large scale hierarchical Mixed-sized designs. 
  3. Sudeshna Kundu(On going): Problem: Rectilinear Steiner Tree construction for congestion driven routing using Pseudo Boolean Satisfiability.
  4. Yagnyasenee Sengupta(On going): Problem: Development of Cyber Physical System for Sustainable waste management system for smart cities using Blockchain.
  5. Sumanta Banerjee (On going): Information Retrieval from online news to estimate and depict the severity of natural disasters. 
MASTERS PROJECT GUIDED: 

  1. PIGP: Plant Inspired Global Placement of Mixed-sized Hierarchical VLSI Circuits.
  2. Placement Solution for Homogeneous FPGA using Tree-based algorithm. 
  3. Smart Healthcare Remote Monitoring System using Internet of Things
  4. Genetic Algorithm Based Sequence Matching 
  5. MaxClique Problem Solving using Boolean Satisfiability and SAT Solver
  6. Global Router for VLSI Circuits based on Quantified Boolean SAT.
  7. Congestion Balancing Global Router
UNDER GRADUATE PROJECT GUIDED: 

  1. Palm Vein Pattern Authentication System
  2. An Alternate Algorithmic Approach to FPGA Placement
  3. Gait Recognition using Segmented Motion Flow Energy Image
  4. Spoken Language Recognition using CNN
  5. Converter Tool For Big Data File Formats
  6. FACEIFY : Text-to-Image translation of Human Faces
  7. Timing Based Side-Channel Attack On FPGA And Countermeasure To Prevent Those Attacks
INSTITUTIONAL RESPONSIBILITIES: Faculty Adviser: M. Tech CSE (Jan – Jun 2020)Faculty Adviser: M. Tech CSE (July – Dec 2019)Faculty Adviser: CSE 8rd SEM (Jan – June 2019)Faculty Adviser: CSE 7rd SEM (Jul – Dec 2018)Faculty Adviser: CSE 6rd SEM (Jan – June 2018)Faculty Adviser: CSE 5th SEM (Jul – Dec 2017)Faculty Adviser: CSE 3rd SEM (Jan – June 2017)BTech Coordinator (July 2017 – till date)DUPC Committee memberMTech Admission Committee memberMTech Syllabus Committee memberInstitute Time-Table coordinatorUniversity Ranking Committee memberNIRF Ranking Departmental CoordinatorNBA Committee memberGymkhana Faculty Adviser (Cricket)Warden, Boys Hostel 9Institute Disciplinary Committee memberDPMC Committee memberFaculty adviser, Machine Learning Club 
DEPARTMENTAL RESPONSIBILITIES:

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